ING Yahir Cante

 -- Simple XNOR gate design library IEEE; use IEEE.std_logic_1164.all; entity xnor_gate is port(   a: in std_logic;   b: in std_logic;   q: out std_logic); end xnor_gate; architecture rtl of xnor_gate is begin   process(a, b) is   begin     q <= a xnor b;   end process; end rtl;

  -- Simple XOR gate design library IEEE ; use IEEE . std_logic_1164 . all ; ​ entity xor_gate is port ( a : in std_logic ; b : in std_logic ; q : out std_logic ); end xor_gate ; ​ architecture rtl of xor_gate is begin process ( a , b ) is begin   q < = a xor b ; end process ; end rtl ;

  -- Simple AND gate design library IEEE ; use IEEE . std_logic_1164 . all ; ​ entity and_gate is port ( a : in std_logic ; b : in std_logic ; q : out std_logic ); end and_gate ; ​ architecture rtl of and_gate is begin process ( a , b ) is begin   q < = a and b ; end process ; end rtl ; ​

  -- Simple OR gate design library IEEE ; use IEEE . std_logic_1164 . all ; ​ entity or_gate is port ( a : in std_logic ; b : in std_logic ; q : out std_logic ); end or_gate ; ​ architecture rtl of or_gate is begin process ( a , b ) is begin   q < = a or b ; end process ; end rtl ;